The present invention relates generally to analog-to-digital converters, and more particularly to a subranging analog-to-digital converter having digitally controlled subranging which eliminates switchable gain and switchable paths in the analog section thereof and further including apparatus for maintaining the prealignment of the various conversion dynamic subranges thereof.
Presently, the need for analog-to-digital converters for 12 or more bits with sample rates in excess of 1 megahertz is increasing, especially for application in such systems as radars and the like. Most converters used for these type applications are falling short of their performance, reliability and manufacturability expectations. The subrange switching and error correction mechanizations of these converters generally appear to be the root of the immediate problems.
Subranging A/D converters rely on an error correction scheme that has very definite and limited tolerance. For the most part, the allowable error is .+-.1/2 quantum at each successive subrange. Accordingly, if a 4-bit quantizer (i.e. 16 quantum levels) is used for the first subrange, the error correction tolerance is 3.125%, if a 6-bit quantizer is used, the error tolerance is 0.78125%, and if an 8-bit quantizer is used, the error tolerance drops to only 0.195%. A dilemma is thus presented to the designer. If a 4-bit quantizer is chosen to take advantage of the ample error tolerance of 3.125%, 4 subranges are generally required for an A/D converter of 12 or more bits with overlap. This results in a series of cascaded wide band amplifiers, switchable attenuators, offset corrections, and a very difficult circuit layout associated therewith. On the other hand, if a 6-bit quantizer is chosen, only 3 subranges are usually needed and likewise, if an 8-bit quantizer is chosen only 2 subranges are needed. But, in either of the latter cases, the designer must work with even tighter error tolerances.
Moreover, A/D converters having four or more subranges are very often time consuming in the prealignment of the subranges and subsequent test debugging. More often than enough, when a calibration adjustment is made to one subrange, it is necessary to go back over the adjustments of the other subranges due to the high degree of inner reactivity of one subrange to another. Consequently, converter mechanizations having many subranges often fall short of their expectations and produce only marginal results.
In one example, if an overlapping bit error correction scheme is used in an A/D converter, the maximum accumulated error that can be tolerated in any subrange is .+-.1/2 quantum, that is, the combined errors resulting from all sources cannot exceed one-half quantum. Taking into account all of the sources of error, it would only be reasonable to place a tolerance of .+-.1/8 quantum on the offset and gain errors of a subrange at the time of realignment which is normally performed at room temperature. This would use up 25% of the error correction capacity for offset and gain and allow 75% of the error budget for all the other combined sources of error. In the case of a 4-bit subrange, the calculation of the alignment tolerance for offset and gain match is 0.78%. For each additional bit the error tolerance will half itself, that is, for bits 5, 6, 7 and 8 the error tolerance will be 0.39%, 0.20%, 0.10%, and 0.05%, respectively. These tolerances don't only involve the subrange reference voltages, but also the relative matching of gain and offset between any two adjacent subranges which is of critical concern. The tolerance given above, for each case, is probably too tight for good manufacturability and reproducibility in a production environment. Therefore, some apparatus may be included in each converter to maintain the subranging prealignment over the variations resulting from time and temperature.